Resume2008
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Current revision (17:02, 22 May 2008) (edit) AndrewPlumb (Talk | contribs) (→A/MS IC Design, EDA and Verification, Cortina Systems, Ottawa, Canada) |
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:'''E-mail:''' [mailto:andrew@plumb.org andrew@plumb.org] | :'''E-mail:''' [mailto:andrew@plumb.org andrew@plumb.org] | ||
::'''Note:''' The first time you e-mail me you'll receive an automated spam queueing message. I actively monitor the queue and white-list the obviously non-spam messages, but you are more than welcome to reply to the message and add yourself as instructed. | ::'''Note:''' The first time you e-mail me you'll receive an automated spam queueing message. I actively monitor the queue and white-list the obviously non-spam messages, but you are more than welcome to reply to the message and add yourself as instructed. | ||
+ | :'''Location:''' Ottawa, Ontario, Canada | ||
:'''See also:''' [http://www.linkedin.com/in/aplumb http://www.linkedin.com/img/webpromo/btn_myprofile_160x33.gif] | :'''See also:''' [http://www.linkedin.com/in/aplumb http://www.linkedin.com/img/webpromo/btn_myprofile_160x33.gif] | ||
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=Experience= | =Experience= | ||
+ | |||
+ | ==A/MS IC Design, EDA and Verification, Cortina Systems, Ottawa, Canada== | ||
+ | |||
+ | :'''Dates:''' February 2008 – Present | ||
+ | |||
+ | ;Responsibilities | ||
+ | |||
+ | :Specification-driven verification of analog/mixed-signal IC designs. | ||
+ | :Behavioural modeling of AMS blocks for accelerated system-level verification. | ||
+ | :Scripted generation of Liberty models (a.k.a. Synopsys dotlib) for complex custom-digital cells. | ||
+ | :General EDA support: | ||
+ | :* Cadence IC, MMSIM and IUS infrastructure. | ||
+ | :* OpenAccess API, SKILL coding, Perl scripting, XML-based document generation (MS Office and custom formats). | ||
==Product Engineer, Cadence Design Systems, Ottawa, Canada== | ==Product Engineer, Cadence Design Systems, Ottawa, Canada== | ||
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:'''Dates:''' November 2003 - December 2007 | :'''Dates:''' November 2003 - December 2007 | ||
- | ;General | + | ;Responsibilities |
- | :* Involved to varying degrees in all Analog Design Environment (ADE-L, XL and GXL) development activities. | + | :Supported the Virtuoso Analog Design Environment (ADE L, XL and GXL) R&D activities. |
- | :** Wrote and revised tutorials communicating new features and fixes to the field. | + | :* Wrote product requirement specification (PRS) documents for new and enhanced capabilities. Coded accompanying mock-ups and functional prototypes where appropriate. |
- | :** Captured issues uncovered during beta testing in forms reproducible by R&D. | + | :* Wrote and edited tutorials communicating new features and fixes to the field. |
- | :** Devised work-arounds for bug and enhancement requests. | + | :* Captured issues uncovered during beta testing in forms reproducible by R&D. |
- | :* Assembled and maintained the databases used for beta testing (IC612_Whatsnew). | + | :* Devised work-arounds for bug and enhancement requests. |
+ | :* Assembled and maintained databases used for beta testing (IC612_Whatsnew). | ||
;Highlights | ;Highlights | ||
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;Responsibilities | ;Responsibilities | ||
- | :Worked in the field demonstrating software, troubleshooting customer issues, conducting workshops and delivering educational services courses. | + | :Worked in the field demonstrating analog/mixed-signal IC electronic design automation (EDA) software, troubleshooting customer issues, conducting workshops and delivering educational services courses. |
- | :Specialized in analog/mixed-signal IC electronic design automation (EDA) software. This included supporting the Analog Design Environment (a.k.a. Analog Artist), schematic capture, mixed-signal simulation using both the Verimix (a.k.a. Spectre-Verilog) and AMS Designer flows and engines, and parasitic back-annotation flows using Diva and Assura extraction results. | + | :Supported the Analog Design Environment (a.k.a. Analog Artist), schematic capture, mixed-signal simulation using both the Verimix (a.k.a. Spectre-Verilog) and AMS Designer flows and engines, and parasitic back-annotation flows using Diva and Assura extraction results. |
;Highlights | ;Highlights | ||
+ | |||
:* Wrote Perl scripts to assist with SpectreHDL to Verilog-A behavioural code translation. | :* Wrote Perl scripts to assist with SpectreHDL to Verilog-A behavioural code translation. | ||
:* Wrote interactive SKILL code to generate schematics from Spectre netlists. | :* Wrote interactive SKILL code to generate schematics from Spectre netlists. | ||
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:'''Dates:''' May 1998 - October 1999 | :'''Dates:''' May 1998 - October 1999 | ||
- | :Reverse engineering ICs for the purposes of patent infringement and competitive analysis. | + | :Reverse engineered ICs for the purposes of patent infringement and competitive analysis. |
- | ==Intern in Microelectronics at CMC Microsystems== | + | ==Intern in Microelectronics at Canadian Microelectronics Corporation== |
:'''Dates:''' May 1997 - May 1998 | :'''Dates:''' May 1997 - May 1998 | ||
- | ::Used to be called ''Canadian Microelectronics Corporation'' | + | ::Now called ''CMC Microsystems'' |
- | :EDA software and fabrication access for the Canadian University community. | + | :Supported EDA software and fabrication access for the Canadian University community. |
:* Supported the use of Analog Artist in the Cadence 97A and IC 4.4.1 releases. | :* Supported the use of Analog Artist in the Cadence 97A and IC 4.4.1 releases. | ||
:* Supported the Gennum GA911 process design kit. | :* Supported the Gennum GA911 process design kit. | ||
- | :* Wrote Perl scripts for submitting Requests For Manufacturing (RFM) from the website instead of by Fax or E-mail. | + | :* Wrote Perl scripts for submitting Requests For Manufacturing Resources (RFMR) from the website instead of by Fax or E-mail. |
=Education= | =Education= | ||
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==Queen's University, Kingston, Canada== | ==Queen's University, Kingston, Canada== | ||
- | :'''Degree:''' B.Sc., Math & Engineering, Control and Communications Systems, September 1992 - December 1997 | + | :'''Degree:''' B.Sc., Math & Engineering, Control and Communications Systems, September 1992 - December 1998 |
+ | |||
+ | :'''Final Year Project:''' DSP Control of a Three-Phase Induction Motor | ||
=Skills= | =Skills= | ||
- | ==General== | + | ==Soft Skills== |
- | * Presenting technical material to a broad range of audiences, including executives (for high-level purchasing decisions), design engineers (the details), and internal R&D (translating customer needs into bug reports and specifications). | + | * Presenting technical material to a broad range of audiences, including executives (for high-level purchasing decisions), design engineers (the technical details), and internal R&D - translating customer needs into bug reports and specifications. |
* Writing formal and informal technical reference material. | * Writing formal and informal technical reference material. | ||
* Creating and delivering presentations via teleconference and screen-capture technologies. | * Creating and delivering presentations via teleconference and screen-capture technologies. | ||
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:* User environment maintenance; launch scripts, batch processing, tweaks and troubleshooting | :* User environment maintenance; launch scripts, batch processing, tweaks and troubleshooting | ||
- | ;Cadence | + | ;Cadence Software |
:* Installation, Licensing, Documentation | :* Installation, Licensing, Documentation | ||
- | :* OpenAccess API | ||
:* Virtuoso | :* Virtuoso | ||
:** DFII | :** DFII | ||
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:** MMSIM Spectre and UltraSim | :** MMSIM Spectre and UltraSim | ||
:** IUS Incisive Analog-Mixed Signal (a.k.a. ''AMS Designer'') | :** IUS Incisive Analog-Mixed Signal (a.k.a. ''AMS Designer'') | ||
+ | :** Verimix (a.k.a. Spectre-Verilog) | ||
==Coding== | ==Coding== | ||
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:SKILL | :SKILL | ||
:XML/XSLT | :XML/XSLT | ||
- | :C/C++ | + | :C/C++, Trolltech's QT API, OpenAccess API, OpenGL API |
- | :QT API | + | |
:Objective-C (via Apple's Xcode IDE) | :Objective-C (via Apple's Xcode IDE) | ||
:Java | :Java | ||
- | :OpenGL | ||
;Hardware Design Languages | ;Hardware Design Languages | ||
- | :Spectre | + | :Spectre, SPICE |
- | :SPICE | + | :Verilog-AMS, VHDL-AMS |
- | :Verilog-AMS | + | |
- | :VHDL-AMS | + | |
==Operating Systems== | ==Operating Systems== |
Current revision
Note: This is a living document. Expect continuous revisions as I pick my words, characterize my skills and pursue new interests.
[edit]
Contact
- Andrew Plumb
- E-mail: andrew@plumb.org
- Note: The first time you e-mail me you'll receive an automated spam queueing message. I actively monitor the queue and white-list the obviously non-spam messages, but you are more than welcome to reply to the message and add yourself as instructed.
- Location: Ottawa, Ontario, Canada
- See also:
[edit]
Objectives
- Primary
- Work for an Ottawa (Canada) based semiconductor design company helping the designers stay current and push the limits of the tools they use.
- Secondary
- Apply my knowledge of analog/mixed-signal IC design theory.
- Obtain my PEO qualifications.
- Keep travel requirements to a minimum.
[edit]
Experience
[edit]
A/MS IC Design, EDA and Verification, Cortina Systems, Ottawa, Canada
- Dates: February 2008 – Present
- Responsibilities
- Specification-driven verification of analog/mixed-signal IC designs.
- Behavioural modeling of AMS blocks for accelerated system-level verification.
- Scripted generation of Liberty models (a.k.a. Synopsys dotlib) for complex custom-digital cells.
- General EDA support:
- Cadence IC, MMSIM and IUS infrastructure.
- OpenAccess API, SKILL coding, Perl scripting, XML-based document generation (MS Office and custom formats).
[edit]
Product Engineer, Cadence Design Systems, Ottawa, Canada
- Dates: November 2003 - December 2007
- Responsibilities
- Supported the Virtuoso Analog Design Environment (ADE L, XL and GXL) R&D activities.
- Wrote product requirement specification (PRS) documents for new and enhanced capabilities. Coded accompanying mock-ups and functional prototypes where appropriate.
- Wrote and edited tutorials communicating new features and fixes to the field.
- Captured issues uncovered during beta testing in forms reproducible by R&D.
- Devised work-arounds for bug and enhancement requests.
- Assembled and maintained databases used for beta testing (IC612_Whatsnew).
- Highlights
- Documented licensing loop-holes to be cleaned up in IC 6.1.1 and IC 6.1.2.
- Initiated exploration into the use of screen-capture for documentation and tutorial purposes.
- Wrote the specification and developed prototypes for revisions to datasheet generation from ADE XL.
- Consulted on the development of SpiceIn, the importing of Spectre and SPICE netlist into DFII.
- Prototyped new and revised existing user interfaces using QT-Designer.
[edit]
Applications Engineer, Cadence Design Systems, Ottawa, Canada
- Dates: October 1999 - October 2003
- Responsibilities
- Worked in the field demonstrating analog/mixed-signal IC electronic design automation (EDA) software, troubleshooting customer issues, conducting workshops and delivering educational services courses.
- Supported the Analog Design Environment (a.k.a. Analog Artist), schematic capture, mixed-signal simulation using both the Verimix (a.k.a. Spectre-Verilog) and AMS Designer flows and engines, and parasitic back-annotation flows using Diva and Assura extraction results.
- Highlights
- Wrote Perl scripts to assist with SpectreHDL to Verilog-A behavioural code translation.
- Wrote interactive SKILL code to generate schematics from Spectre netlists.
- Wrote multiple programs for Spectre and SPICE netlist to Verilog-AMS conversion.
- The first few iterations were written in Perl.
- The final example was a two-stage approach written in Java. The netlist parsers were written in JavaCC to convert Spectre and SPICE netlists into an XML intermediate format, then used XSL Transforms to translate from the XML into the final destination format.
- Prototyped an early example of AMS-in-ADE support. The code generated an initial AMS Designer configuration from existing Spectre states in ADE.
[edit]
Design Analysis Engineer, Chipworks, Ottawa, Canada
- Dates: May 1998 - October 1999
- Reverse engineered ICs for the purposes of patent infringement and competitive analysis.
[edit]
Intern in Microelectronics at Canadian Microelectronics Corporation
- Dates: May 1997 - May 1998
- Now called CMC Microsystems
- Supported EDA software and fabrication access for the Canadian University community.
- Supported the use of Analog Artist in the Cadence 97A and IC 4.4.1 releases.
- Supported the Gennum GA911 process design kit.
- Wrote Perl scripts for submitting Requests For Manufacturing Resources (RFMR) from the website instead of by Fax or E-mail.
[edit]
Education
[edit]
Queen's University, Kingston, Canada
- Degree: B.Sc., Math & Engineering, Control and Communications Systems, September 1992 - December 1998
- Final Year Project: DSP Control of a Three-Phase Induction Motor
[edit]
Skills
[edit]
Soft Skills
- Presenting technical material to a broad range of audiences, including executives (for high-level purchasing decisions), design engineers (the technical details), and internal R&D - translating customer needs into bug reports and specifications.
- Writing formal and informal technical reference material.
- Creating and delivering presentations via teleconference and screen-capture technologies.
- Working with globally-dispersed teams of people.
[edit]
EDA
- General
- UNIX System administration
- Data management infrastructure
- Distributed simulation infrastructure
- User environment maintenance; launch scripts, batch processing, tweaks and troubleshooting
- Cadence Software
- Installation, Licensing, Documentation
- Virtuoso
- DFII
- Analog Design Environment (a.k.a. Analog Artist), including new XL and GXL technologies.
- Schematic Capture
- Parasitic back-annotation and re-simulation flow
- Simulation
- MMSIM Spectre and UltraSim
- IUS Incisive Analog-Mixed Signal (a.k.a. AMS Designer)
- Verimix (a.k.a. Spectre-Verilog)
[edit]
Coding
- Programming Languages
- SKILL
- XML/XSLT
- C/C++, Trolltech's QT API, OpenAccess API, OpenGL API
- Objective-C (via Apple's Xcode IDE)
- Java
- Hardware Design Languages
- Spectre, SPICE
- Verilog-AMS, VHDL-AMS
[edit]
Operating Systems
- Linux
- User by choice since 1993
- Broad range of distributions: Slackware, Fedora Core, Red Hat Enterprise, Linux From Scratch, Gumstix Embedded
- Mac OS X
- User by choice since 2006
- Parallels-hosted Linux installations
- Microsoft Windows
- User out of necessity since 1992
- Microsoft Office applications; particularly interested in XML data formats for automating documentation flows
- Other UNIX (Solaris, HPUX)
- User since 1992; administration since 1999
[edit]
References
- Available on request.